| 摘要 |
PURPOSE:To reduce the generation of carriers due to an impact ionization, to impress the change of the potential of a section where one of carriers generated is integrated at a minimum even on the integration of one of carriers generated in the first conduction type semiconductor layer and to increase the conductance of a MOSFET by extending a depletion layer in a second conduction type second semiconductor layer and weakening the field strength of the depletion layer. CONSTITUTION:A low-concentration N<+> impurity layer 8 extends a depletion layer in a high-concentration N<+> impurity layer 3 for a drain and weakens field strength in the depletion layer, and reduces the generation of carriers causing the lowering of source-drain withstanding voltage. A high-concentration P<+> impurity layer 9 prevents the lowering of built-in voltage between a high-concentration N<+> impurity layer 2 for a source and a P-type silicon substrate 1 even when holes in carriers generated are integrated to the front surface of the high-concentration N<+> impurity layer 2 for the source, and obviates the inflow of electrons to the P-type silicon substrate 1 from the high-concentration N<+> impurity layer 2 for the source. Accordingly, the increase of withstanding voltage, that is, fining-of a MOSFET is realized, and reliability is improved. |
