| 摘要 |
To accelerate the image processing of binary images, hard-wired logic circuits are provided by means of which the image information items are processed line by line. Hard-wired logic circuits and sequences for determining edge points of an object are specified. Features of the object which are obtained by summing together a quantity, for example the brightness, over all pixels of the object are stored as partial sums allocated to the individual pixels. The relevant feature is then formed by summation of the partial sums of the edge points. <IMAGE> |
