| 摘要 |
PURPOSE:To prevent an accumulation of a soft error and read and write an information at high speed by correcting an information error making the contents of a counter stepping every time when an X direction address selecting a matrix shape memory array is inputted as a Y direction address. CONSTITUTION:Synchronizing with a fall edge of a low address strobe reversing RAS, during a refresh mode, external X direction addresses A1R-AnR are successively fetched. At the same time, every fetching, a clock from a basic clock generating circuit 16 is counted, Y direction addresses A1C-A(n-m)C are outputted, the contents of plural dynamic RAM cells of a memory array 11 are read and an error correction is done in a decoding correction circuit 19. The refresh by these writings is executed synchronously with the fall edge of the strobe reversing RAS. Accordingly, the refresh can be done during the reading and the writing periods, an accumulation of a soft error can be prevented, the writing and reading speed requiring no error correction is similarly very high to that having no error detection and correction. |
