| 摘要 |
PURPOSE:To reduce the area of a cell markedly by forming the internal circuit which includes the cell which is so constituted that a potential of the substrate is supplied from its back side on which either of the two transistors is arranged and which is not connected to an external signal line directly. CONSTITUTION:For a basic cell 9a, a substrate potential is supplied from the back side of substrate not shown in the drawing. In this constitution, a contact region for substrate is eliminated and further the part of a contact region for impurity well which is present on a boundary with the adjacent basic cell 9 is changed into a contact region 7a for impurity well of the pattern converged in the left part in the drawing. The distance of MIS-FET 4 and that of 6 between the adjacent basic cells 9a are reduced. Consequently an area of the basic cell 9a is reduced about 30% compared with that of the basic cell 9 so that the enhancement of integration of a gate array becomes possible by that amount of the reduction. |
