| 摘要 |
PCT No. PCT/DE85/00118 Sec. 371 Date Aug. 21, 1985 Sec. 102(e) Date Aug. 21, 1985 PCT Filed Apr. 16, 1985 PCT Pub. No. WO85/05497 PCT Pub. Date Dec. 5, 1985.A semiconductor arrangement is suggested which is provided with a capacity transistor and a drive transistor in form of a Dralington-circuit. Thereby, the two transistors are monolithically integrated with a planar technique in a common substrate (8), which forms the two collector zones of the two transistors (T1,T2). A passivation layer (14) covers the main face of substrate (8) covering this main surface with the exception of contact windows. A cover electrode (13) is disposed above the passivation layer in the area between the collector zone and the base zone (4) of the capacity transistor (T2), whereby this passivation layer is connected with a resistor strip (2) at a distance from the base zone (4) for adjusting its potential. An additional guard strip (3) is diffused into the main surface between the resistor strip (2) and the base zone (4). In order to prevent a voltage rupture in the area of the resistor strip (2), the passivation layer is designed thinner at the area adjacent the base zone (4) than in the remaining area beneath the cover electrode (13). |
