| 摘要 |
A racefree CMOS clocked logic circuit includes a first CMOS clocked gate for selectively transferring an input signal according to a first clock pulse and providing an interstage signal corresponding to the input signal; and a second CMOS clocked gate, which is connected directly to the first CMOS clocked gate, for selectively transferring the interstage signal according to a second clock pulse and providing an output signal corresponding to the interstage signal. The operation of first CMOS clocked gate is synchronized to the first clock pulse, and the operation of second CMOS clocked gate is synchronized to the second clock pulse. The second clock pulse is in-phase with or identical to the first clock pulse so that signal races between the input signal and the output signal are eliminated.
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