| 摘要 |
PURPOSE:To eliminate unnecessary data transmission by allowing a subordinate CPU to judge that a subordinate CPU is in a runaway state when a signal for resetting the wait state of a main CPU is sent out continuously at the end of input/output operation and then stop subsequent data transmission. CONSTITUTION:When the main CPU accesses the subordinate CPU, a signal SET is generated to set a latch LAT3 and a one-shot multivibrator OM1, and a wait signal for the main CPU is generated. While the subordinate CPU is in normal operation, a wait clear signal CLEAR is generate at the end of input/ output operation and a latch LAT3 is reset through a latch LAT4 and a gate G2 to reset the wait signal WAIT, but when a subordinate CPU which is not present is accessed and the signal CLEAR is sent out continuously, the latch LAT4 is cleared at the fall of the signal SET and the LAT3 is also cleared through the gate G2, thereby resetting the signal WAIT. |
