| 摘要 |
PURPOSE:To transmit data with high efficiency by switching the stage position of a shift register which delivers an output when the double reading or misreading is caused by a bit slip through a selection circuit. CONSTITUTION:If the count value Qm of a counter CNTR 4 is defined as (a) in a normal state, the output Qa of a shift register SR 2 is selected and delivered by a selector SEL 3. Here the input UPEN of the counter CNTR 4 is set at '1' with the count value Qm of the CNTR 4 set equal to (a+1) if a writing slip occurs. Thus the output of the SEL 3 is changed to Qa+1 from Qa of the register SR 2. Therefore the data DOUT' delivered with the timing set before said change of the output is also delivered with the timing obtained after the change. Thus the same data is read twice to the DOUT', and the misreading due to a bit slip at the writing side is corrected. As a result, the original data format is not broken although a bit error occurs.
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