| 摘要 |
PURPOSE:To miniaturize a parallel multiplier together with reduction of the power consumption and a high-speed operation by selecting one of five inputs of a basic cell in response to the combination of logical levels of three selection control signals and using the selected input as the augend input of a full adder. CONSTITUTION:Plural basic cells 20 are arrayed two-dimensionally based on the multiplicand data and the multiplier data. The digit data Xi and Xi' of the multiplicand data corresponding to the cells 20 and data (Xi-1) and (Xi-1)' lower than data Xi and Xi' by a bit are supplied via data lines 23-26. The cells 20 select one of outputs of the four inputs given from the lines 23-26 and an input of a fixed level in response to the inputs of selection control signals S(X), S(2X) and S(M) given from control lines 281-283. This selected output is supplied to an augend input terminal Xin of a full adder 10. The addend output and the carry output of the cell 20 at the preceding stage are applied to an addend input terminal Sin and a carry input terminal Cin of the adder 10 through terminals 11 and 12 respectively. |
