| 摘要 |
<p>PURPOSE:To improve the transmission efficiency of data by producing a reset signal delayed by its width through a bit buffer device and resetting an FF in a slip detecting circuit at the fall of said reset signal. CONSTITUTION:A reset signal RST is delayed by a delay circuit 33 by the time twd equal to the width the signal RST in a slip detecting circuit 3'. Thus a delayed reset signal RSTD is obtained. This signal RSTD has a fall at the end of the signal RST and resets FF 26-29. Then the write clock WCK and the signal RST are impressed twice to the FFs 26 and 27 of FFs 28 and 29 before these FF are reset by the signal RSTD. Thus said FFs 26 and 27 or FFs 28 and 29 deliver the write bit slip signal WSLIP or the read bit slip signal RSLIP (='1'). However these signals are cleared by the signal RSTD. Therefore the circuit 3' can detect a malfunction that is produced with input of the clock WCK for a period when the signal RST, etc. exist.</p> |
