| 摘要 |
PURPOSE:To allows a module which time elapse after requesting is long to use a bus by sending bus use requests from respective modules to a priority determining circuit through a direct route, a flip-flop route, or a buffer route. CONSTITUTION:Bus use request signals REQ10-REQn from plural modules connected to the common bus are inputted to a priority circuit 4 directly through a multiplexer 8 when flip-flop routes 6 passed through flip-flops 6A and 6B are both free to obtain bus use permission signals GNT0-GNTn, but when one of the flip-flop routes is not free, they are sent to the other free route and enqueued temporarily. When either of the routes is free, they are sent to a buffer route 7 including a buffer 10 to wait for a flip-flop route 6 to become free, and sent to the route which becomes free through multiplexers 8A and 8B. |
