发明名称 TIMING GENERATING CIRCUIT
摘要 PURPOSE:To set a binary (n) stage counter to an optional value in a short time, and also by a small number of external input terminals, and to execute easily a test by constituting said counter so that it can be switched to a binary (n) stage counter operation and an operation of an (n) stage shift register. CONSTITUTION:At the time of a regular operation, a circuit function switching terminal 6 and a test use input terminal 7 are fixed to H. In this state, when a reset pulse is inputted, outputs Q of (n) pieces of D-FFs 2 all become L. Subsequently, when a clock is inputted, the output Q of the D-FF 2 of the first stage is changed to H by its rise, and the outputs Q of the D-FFs 2 of the second stage and thereafter are inverted by a rise of the clock, only when the output Q of the D-FF 2 of one stage before is H. Accordingly, outputs of (n) pieces of D-FFs 2 show a binary number of until 2<n>-1. At the time of a test mode, the terminal 6 is fixed to L, and an output of a test use circuit 3 always becomes L, therefore, to the D-FF 2 of the first stage, an input value from the terminal 7 is inputted as it is, and to the following D-FFs 2, a value of the output Q of one stage before is inputted, therefore, (n) pieces of D-FFs 2 constitute (n) stages of shift registers.
申请公布号 JPS61212112(A) 申请公布日期 1986.09.20
申请号 JP19850051951 申请日期 1985.03.15
申请人 NEC CORP 发明人 HIRAO EIJI
分类号 G11C19/28;G06F1/04;G06F1/06;H03K5/135;H03K5/15 主分类号 G11C19/28
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