| 摘要 |
PURPOSE:To use a dynamic type delayed flip flop and reduce a chip area by providing a means for making a multi-purpose clock being not 'H' level at the same time during an operation and being 'H' level only during a stand by. CONSTITUTION:A timing signal 8 is not used directly as phi1 signal of a logic circuit 10 and through an OR gate 23, impresses a stand by signal 11 to this OR gate 23. In an operating condition (interval T1), since the stand by signal 11 is 'L' level, the timing signal 11 is used as a clock of the logic circuit 10 as it is. During a stand by mode, since the stand by signal 11 is 'H' level, an output of the OR gate 23 goes to 'H' level. Accordingly, even if a dynamic type delayed flip flop is used in the logic circuit 10, phi1, phi2 go to 'H' level, so that an input level of an inverter does not go to an intermediate level but is maintained in a correct input level. |
