| 摘要 |
<p>PURPOSE:To make an exclusive bus and momentary stopping of a counter unnecessary by providing a timing data holding circuit that reads and stores a part of a reading signal of timing data given to a timer. CONSTITUTION:Timing data of 12 bits is stored in a counter 11 and data 12 of high-order 8 bits is sent to an internal data bus 14 by a reading signal RD. Data 13 of low-order 4 bits is sent out to a holding circuit 15 consisting of 4 bit register by the reading signal RD and held. The reading signal RD is outputted at 1 cycle of a timer reading instruction, and the reading signal RD is given to the gate of output side of the holding circuit 15 at the next 2 cycles. The held content is read out there and sent out to the data bus 14.</p> |
