发明名称 LOGIC ANALYZER DEVICE
摘要 PURPOSE:To allow an investigator to recognize properly a signal having an unstable logical state by comparing and discriminating an input signal with two high and low thresholds. CONSTITUTION:By setting a signal level indicating switch 2, a threshold circuit 11 generates a high level threshold signal and a low level one and transmits them to a probe 3. It compares the input signal with high and low level threshold signals and stores the discriminated signals in a high level memory 12 and a low level memory 13, respectively, by setting a memory clock switch 4. In order to investigate the logical state of a device to be tested, the probe 3 is set, and a clock period to be stored is also set by the memory clock switch 4, after which the logical signal level is set. Then the levels of signals, which are inputted to the preset probe when the device to be tested operates, are discriminated by their thresholds, and stored in the signal level memory circuits 12 and 13.
申请公布号 JPS61210963(A) 申请公布日期 1986.09.19
申请号 JP19850052745 申请日期 1985.03.15
申请人 NEC CORP 发明人 KAWAGUCHI TORU
分类号 G01R13/28;G01R13/20 主分类号 G01R13/28
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