| 摘要 |
PURPOSE:To monitor without increasing a burden of a hard and a soft by latching a data flowing between a main CPU unit and a sub CPU unit by a latch clock and writing successively in a memory circuit by a produced address. CONSTITUTION:A data delivered between a main CPU unit 1 and a sub CPU unit 2 is a message type in which a master station, an address, and an information and the like are set at predetermined positions and comprises plural bytes. A transmitting and receiving of the data makes an interruption of a timer and the like a trigger and is carried out at a fixed cycle. When the data is fed from the main CPU unit 1 to the sub CPU unit 2, by an address bus, a sub CPU unit of the other party is designated, a data is transmitted to a common bus 3 and of control signals, a writted in a data exchanging memory 4 of the relevant sub CPU unit 2. Similarly when reading the data, the unit 2 is designated, a read signal of the control signals is outputted and from the data exchanging memory 4 of the relevant sub CPU unit 2, the data is read. |
