| 摘要 |
PURPOSE:To shorten the fixed and floating point converting by providing a shift register and a down counter to write the complement data of the fixed point, comparing the code of the above-mentioned complement data and the output of the highest bit area, shifting the contents of the down counter and the shift register until both are dissident and obtaining the floating point data. CONSTITUTION:When the code of the data written in a shift register 2 is coincident to an MSB of the highest order bit, the output of an output inverting type OR circuit 4 goes to be '1', and a clock is outputted from a NAND circuit 3. The clock counts down a down counter 1 and the register 2 is shifted to the left. The action is continued until the output of the circuit 4 goes to be a zero level. When the data written in the register 2 are all 0, a zero detecting circuit 5 detects and the converting action is not executed. Thus, the exponent part of the floating point type is stored in the down counter 1 and the mantissa part is stored in the shift register 2. |
