发明名称 CONSTANT VOLTAGE CIRCUIT
摘要 PURPOSE:To output the stable constant voltage with a power source voltage only by providing a MOS transistor to operate at the linear area between the inverter to invert the prescribed bias voltage and a constant voltage output terminal. CONSTITUTION:The symbol Q 18 is provided between an inverter INV 1 composed of MOS transistors Q 16 and Q 17 and a constant voltage output terminal T, and a power source voltage VCC is impressed to the gate. The symbols Q 11, Q 12, Q 13, Q 14 and Q 15 in a bias voltage generating circuit BV 1 is operated at the saturating area since the gate is connected to its drain, and respective Qs are operated in the same manner as the resistance. Consequently, the voltage of a connecting point N 11 is changed in accordance with the change of a voltage VCC. The voltage of a connecting point N 12, which passes through the INV 1, is also changed in accordance with the change of the voltage of the connecting point N 12, and since the Q 18 is operated at the linear area, the voltage is absorbed and at the output terminal T, a constant voltage is obtained.
申请公布号 JPS61210409(A) 申请公布日期 1986.09.18
申请号 JP19850051019 申请日期 1985.03.14
申请人 TOSHIBA CORP 发明人 KATSUMATA HIDEKAZU
分类号 G05F3/24 主分类号 G05F3/24
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