| 摘要 |
PURPOSE:To improve a processing speed of a microprogram during a transfer of an interlock by providing a data buffer primary control circuit to prevent a generation of overrun during a transfer of a data streaming mechanism. CONSTITUTION:A data buffer priority degree control circuit 40 comprises JKFFs 41, 42 and AND circuits 440, 450. When a data transfer is performed by a data streaming mechanism (DSF), a data transfer mode signal DSF is turned on. Thereby the AND circuits 440 and 450 are activated, a channel side access permission signal is outputted through a JKFF 41, an AND circuit 440, an OR circuit 442 and the channel side has priority. During a transfer of an interlock, AND circuits 441, 451 are activated. When there is an access request from a microprogram side, the access permission signal is outputted to the microprogram side. Thereby, the generation of an overrun during the transfer of the DSF is prevented and a processing speed of the microprogram can be improved. |
