Reset delay circuit for an electronic postage meter.

摘要

An electronic postage meter with a circuit (80) to provide for a delay period before operation of a postage meter is disclosed. The circuit (80) provides a fixed delay which is triggered when three input signals provided to the circuit (80) become active. The input signals will be active in this embodiment to indicate satisfactory regulated voltage level, a satisfactory unregulated voltage level, and a satisfactory external clock frequency respectively. The output of the delay circuit (80) upon acceptance of these active signals provide a reset delay signal to a system processor (30) and also controls the signals that are provided to the non-volatile memories (50,60) and the system printer (70). The circuit (80) uses advantageously logic devices to provide the delay of the output signal rather than the traditional utilization of R-C network. The delay circuit (80) is particularly useful in a system such as postage meter that utilizes a microprocessor (30) and a non-volatile memory (50, 60), to protect the contents of the non-volatile memory.