发明名称 MEMORY CIRCUIT
摘要 <p>PURPOSE:To obtain a stable required voltage by arranging so that a circuit pulling up a pair of bit lines to an electric source formed by a MES FET having the source and the gate shorted and a diode having the anode connected with the gate side between the ground and the gate of the MES FET. CONSTITUTION:The depletion type MES FET Q7, Q8 with the gate and the source short-circuited has its gate connected to the ground by diodes D1, D2. The potential of bit lines B1, B2 is limited to the forward voltage (0.6-0.7V) and is not raised above this value. A word line W goes H so that transistors Q5, Q6 are turned on. When a memory cell MC is selected, assuming that the transistor Q1 is on and transistor Q2 is off for this memory cell, the bit line B1 is lowered to ground potential through Q5, Q1 while the bit line falls to 0V by the voltage drop at the transistor Q7. Since there is no pull down by Q6, Q2 in the bit line B2, it is maintained at the non-select level of 0.6-0.7V. In such a manner, gate burning or memory data destruction may be prevented under excess bit line potential.</p>
申请公布号 JPS61208693(A) 申请公布日期 1986.09.17
申请号 JP19850048791 申请日期 1985.03.12
申请人 FUJITSU LTD 发明人 SUYAMA KATSUHIKO
分类号 G11C11/34;G11C11/40;G11C11/41;G11C11/417 主分类号 G11C11/34
代理机构 代理人
主权项
地址