| 摘要 |
PURPOSE:To obtain a stably phase locked signal with high accuracy and to reduce remarkably the scale of a delay circuit by setting a delay time circulating a phase locked loop within a prescribed range using a period of a reference signal. CONSTITUTION:A fixed oscillator 20 is operated in a frequency being an integral number (N) times of a frequency fi of the reference signal Si and sends its output to a delay circuit 21. The circuit 21 generates m-set of signals having a prescribed phase difference to input them to a phase switching circuit 15, a data selector 14 of the circuit 15 selects sequentially one signal in response to the phase of the signal Si among the m-set of signals and inputs the signal to a frequency divider 23 having 1/n frequency division. The frequency divider 23 inputs the signal So subject to 1/n into a phase comparator 11. The comparator 11 inputs a phase difference signal between the signals Si and So to a control pulse generating circuit 12, which inputs the output pulse to an up/down counter 13 of the circuit 15 to form a phase locked loop. The delay time (t) circulating through the phase locked loop is set to be in the relation expressed in equation I by using a period T of the signal Si. Thus, a stable phase locked signal with high accuracy is obtained.
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