| 摘要 |
PURPOSE:To significantly improve a system throughput by providing a circuit for storing a line address accessed from the system side and a circuit inhibiting the refresh operation of the line when the address for the line is outputted from an address counter for refreshing. CONSTITUTION:When the line address is inputted to an access state memory 36 with accessing from the system side, a controller 38 associated with the memory 36 writes '1' in a bit of the designated address. That is, the line address accessed by the system is indirectly stored. The controller 38 sends a refresh permit signal to a refresh controller 28 when the data read from the access state memory 36 is '0'. When it is '1', the controller supplies a refresh inhibit signal while clearing the '1' data in the memory 36 to '0'. The refresh controller 28 executes a refresh operation when receiving the permit signal and does not perform refreshing when receiving the inhibit signal. Thus, the system throughput is improved significantly.
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