| 摘要 |
PURPOSE:To enable writing and reading to be performed independently by providing a multiplexer for selectively sending to a memory one of the outputs of writing and reading address counters and a controller executing writing and reading independently. CONSTITUTION:The writing address counter 20 and the reading address counter 30 generate a writing address WRADR and reading address RDADR from clock signals VCLK and RCLK from the controller 60. An up/down counter 40 counts up when a mode signal RW is in the write mode and counts down when it is in the read mode. The multiplexer 50 supplies the output WRADR of the write address counter 20 to the memory 10 and supplies the output RDADR of the read address counter 30 when in the read mode. The controller 60 is formed by using sequential circuit and fuse logic. In such a manner reading and writing can be performed independently.
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