发明名称 EVALUATING METHOD FOR MIS TYPE SEMICONDUCTOR DEVICE
摘要 PURPOSE:To evaluate a semiconductor-insulating interface by setting the source or drain potential of a first MISFET through the first MISFET with a gate region to be tested and second and third MISFETs sharing a source or a drain. CONSTITUTION:A MISFET to be tested is measured initially in such a manner that gate electrodes 3 and 4 for MISFETs are brought to an open state and voltage-capacitance are measured between a gate electrode 2 for the MISFET to be tested and a semiconductor substrate 9. Voltage sufficiently higher than the threshold is applied to the gate electrodes 3 and 4 for the MISFETs after the completion of measurement. A source or a drain 7 and 8 are brought to ground potential. The temperature of the MISFET to be tested is kept constant, a predetermined electric field is applied to the gate electrode 2, and the MISFET to be tested is held for a prescribed period. The MISFET to be tested is returned to room temperature after the prescribed period passes, and voltage is removed from the gate electrodes 2, 3, 4 for the MISFETs. Voltage- capacitance characteristics are measured between the gate electrode 2 for the MISFET to be tested and the semiconductor substrate 9, and compared with said characteristics.
申请公布号 JPS61208269(A) 申请公布日期 1986.09.16
申请号 JP19850050040 申请日期 1985.03.13
申请人 MATSUSHITA ELECTRONICS CORP 发明人 TATSUUMA KENICHIRO
分类号 H01L29/78;H01L21/66;H01L21/822;H01L27/04 主分类号 H01L29/78
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