| 摘要 |
An arbitration circuit comprises a plurality of enabling elements which determines when predetermined conditions exist to transmit a request signal. A first gate combines transmitted request signals to generate a combined request signal. A plurality of first latches, each first latch having a sequential priority order and operatively connected to a corresponding enabling element, and further connected to the output of the first gate, generates an enable and a disable signal. A plurality of second gates is included, each second gate is operatively connected to the first gate to receive the combined request signal, and each second gate operatively connected to the corresponding first latch to receive the enable signal. Further, each of the second gates is operatively connected to each first latch having a higher sequential priority to receive the disable signal from each of the higher sequential priority first latches, each of the second gates generating a select control signal corresponding to the request signal selected by the arbitration circuit, thereby permitting a requestor access to the bus.
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