| 摘要 |
PURPOSE:To obtain a small-sized and high withstand-voltage CMOS semiconductor device having a large withstand quantity to latch-up by a method wherein low-impurity concentration channel stopper regions are provided on the whole surfaces of parts of the semiconductor substrate, which are located under the field oxide films on the substrate, and high-impurity concentration guard regions are provided in the channel stopper regions separatedly from the source and drain regions of the MOS transistors. CONSTITUTION:Channel stopper regions 14 are provided on the whole surfaces of parts of a semiconductor substrate 1, where are located under fixed oxide films 3 on the substrate 1, and guard regions 16 are formed in the channel stopper regions 14 separatedly from the source and drain regions 4 and 5 of an MOS transistor 8, while channel stopper regions 15 are provided on the whole surfaces of parts of the semiconductor substrate 1, where are located under the field oxide film 3 on one side and one more field oxide film 3 on the substrate 1, and guard regions 17 are formed in the channel stopper regions 15 separatedly from the source and drain regions 9 and 10 of an MOS transistor 13. As the guard regions 16 and 17 are provided separatedly from the source and drain regions 4, 5, 9 and 10 of the MOS transistors 8 and 13, the guard regions 16 and 17 can be set in a high impurity concentration regardless of the junction withstand voltage, the potentials of the semiconductor substrate 1 and a well region 2 are favorably fixed and the withstand quantity to latch-up can be increased. |
