| 摘要 |
PURPOSE:To improve device performances such as low on-resistance, mutual conductance and switching speed and to reduce the chip area, by improving the source electrode taking-out opening section so as to attain a larger channel width within a given chip area. CONSTITUTION:Planar configuration of a second semiconductor layer 4 above a first semiconductor layer 2 have pattern portions 12A-12C of a polygon having sides of integer multiplication of two, for example an octagon. At least one of the pattern portions 12A-12C is smaller than another ones and two coupling patterns 12D, 12E narrower than the polygonal pattern portions connect them with each other. At least one semiconductor layer of electrode taking-out opening sections exposed in the patterns 12A-12C is an N<+> type semiconductor layer, and in another patterns 12A, 12B there exist both of a P<+> type semiconductor layer and N<+> type semiconductor layer. On the basis of this combination, the pattern 12C having the N<+> type semiconductor layer exposed is made smaller than another patterns 12A, 12B. |
