| 摘要 |
In the fixed addition-value circuit according to the subject matter of the invention, the odd summands 1 and 3 and 5 and 7 and 9 are processed decremented by the number 1 in both input ranges and thus the number of required sum-and circuits is decreased to 25. The wrong result numbers are corrected by means of two up-shifting circuits which are combined with a linear circuit and are arranged at the end of this fixed addition-value circuit. The first up-shifting circuit is a two-up-shifting circuit which raises the number present at its inputs by the number 2 in the case of shift activation. The second up-shifting circuit is a one-up-shifting circuit which raises the number present at its inputs by the number 1 in the case of shift activation. These shift circuits are controlled by means of a binary half-adder 20. <IMAGE>
|
