| 摘要 |
PURPOSE:To set freely the phase difference between input and output frame pulses within a time range proportional to the number of concentrated insignificant bits of both input and output frames, by controlling a RAM through a 3-state buffer and avoiding the collision between write and read modes. CONSTITUTION:Each input/output terminal Di of RAM 1 and 2 of capacity M words respectively is connected in common to an input data line 101. A clock input terminal CLK of a counter 3 of L bits it connected to a clock line 102 at the input side with an initialization input terminal R connected to an input frame pulse line 103. A 3-state buffer of L bits transfers the output of the counter 3 to the RAM 1, and a 3-state buffer 10 of L bits transfers the output of a counter 4 to the RAM 1. While 3-state buffers 11 and 12 of L bits transfer the outputs of counters 3 and 4 to the RAM 2 respectively. Then 3-state buffers 13 and 14 of one bit transfer the outputs of RAM 1 and 2 to a data output lines 112 respectively. |
