| 摘要 |
A testing technique is disclosed for assuring AC performance of high speed random logic, employing a low speed tester. AC testing on a low speed tester is split into multiple phases. During the first phase, a slack time delta is introduced, which is the time difference between the product cycle time required by the application and the tester cycle time used in the product test. The product is tested with this timing using conventionally generated test patterns. The effect of the slack is then resolved in the subsequent phases of the test. The product is tested again with the same type test patterns as in the first phase, but with redefined strobe times at the staging latches in the circuit. The slack delta is transferred to paths between the consecutive staging latches and the resultant signals arrive and get sampled by the low speed tester as if there were no slack. The principle of the invention can be applied to any logic circuit to be tested, which has two or more staging latches or to logic circuits which have a plurality of N combinatorial logic blocks each separated by respective staging latches from the others. |
