| 摘要 |
In the fixed addition value circuit according to the subject matter of the invention, the odd summands 1 and 3 and 5 and 7 and 9 are processed decremented by the number 1 in an input range. In the other input range, the summands 0 to 2 are processed as 0 and the summands 3 to 5 are processed as 3 and the summands 6 and 7 are processed as 6 and the summands 8 and 9 are processed as 8. In this manner, the number of required sum AND circuits is lowered to 20 in this fixed addition-value circuit. The wrong result numbers are also corrected by means of two up/shift circuits which are combined with a linear circuit. The first up/shift circuit is a one-up/shift circuit with 20 AND circuits having 2 inputs each. The second up/shift circuit is a two-up shift circuit which also has 20 AND circuits having 2 inputs each. <IMAGE>
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