发明名称 OUTPUT BUFFER CIRCUIT
摘要 PURPOSE:To output lots of electric signals from the inside of an IC externally without increasing external terminals of the IC by combining two P, N-channel MOSFETs and four gate circuits respectively. CONSTITUTION:When a level of a control signal C1 is logical '0', QP1, QP2, QN1, QN2 are all turned off and an output '0' of an output buffer circuit is in the state of high impedance. When the level of the signal C1 is logical '1' and both input signals I1, I2 are logical '0', zero potential to turn on the QN1 is outputted from the output O. When the input signals I1, I2 are logical '0', '1', a voltage adding a threshold voltage of the QP2 to zero potential is outputted from the output O to turn on the QP2. When the input signals I1, I2 are logical '1', '0', a voltage subtracting a threshold voltage of the QN2 from a voltage VCC is outputted to turn on the QN2 from the output O. When the input signals I1, I2 are logical '1', '1', the voltage VCC is outputted from the output O to turn on the QP1. That is, four output states are obtained to four logical state of the input signal.
申请公布号 JPS61203717(A) 申请公布日期 1986.09.09
申请号 JP19850044321 申请日期 1985.03.06
申请人 NEC CORP 发明人 YASUDA SADAHIRO
分类号 H01L21/8238;H01L27/092;H03K19/0175;H03K19/173 主分类号 H01L21/8238
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