发明名称 |
Digital data synchronizing circuit |
摘要 |
A circuit for reproducing a signal associated with synchronization with a digital data signal. The digital data signal includes a combination of a plurality of pulses each having a predetermined pulse width. The reproducing circuit comprises a logic circuit for discriminating the pulse width of at least one of the plurality of pulses, an oscillator and a frequency divider connected with the oscillator and responsive to the output of the logic circuit to generate a clock signal timed with the output of the logic circuit.
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申请公布号 |
US4611335(A) |
申请公布日期 |
1986.09.09 |
申请号 |
US19820422190 |
申请日期 |
1982.09.23 |
申请人 |
HITACHI, LTD. |
发明人 |
ARAI, TAKAO;KOBAYASHI, MASAHARU;TAKEUCHI, TAKASHI;OKUBO, EIJI;ENDOH, HIROSHI |
分类号 |
G11B20/10;G11B20/14;H04L7/033;H04L7/04;(IPC1-7):H04L7/02 |
主分类号 |
G11B20/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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