| 摘要 |
PURPOSE:To improve the performance of an information processor by reducing the delay time of an address conversion circuit after comparing an input address with the difference between the upper limit and bottom addresses. CONSTITUTION:An input address VA is stored in an address register 12, and the difference between the upper limit address ULA and the bottom address BA is calculated previously by an address difference calculating means 10. Then this address difference is stored in an address difference memory means 11a. The sum of both addresses VA and BA is calculated by an address sum calculating means 13. An address comparison means 14 compares the address VA with the output address of the means 11a. A check result flip-flop 15 is set with the output of the means 14.
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