发明名称 DIGITAL PHASE LOCKED DEVICE
摘要 PURPOSE:To obtain the gain which is free from a blind sector by providing a code discriminator for phase error signal and an addition circuit which adds the output of said code discriminator to an osillator in addition to an attenuator applying the bit shift. CONSTITUTION:A code discriminator 9 delivers '1' and '0' when the phase error signal phie is positive and equal to '0' or negative respectively. Then the signal phie is positive with the increase of the input phase signal phii, and the output value '1' of the discriminator 9 is added to the value bit-shifted by an attenuator 2 and then suppliedd to an oscillator 13. Thus the output phase signal phigamma is increased. The signal phie is negative with decrease of the signal phii. In this case, the output of the discrimonator 9 is equal to '0' and therefore only the output of the attenuator 2 is substantially supplied to the oscillator 13. Therefore the signal phigamma is reduced. Here the gain obtained from the combination of the attenuator 2 and the discriminator 9 has no blind sector.
申请公布号 JPS61202378(A) 申请公布日期 1986.09.08
申请号 JP19850043132 申请日期 1985.03.05
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIMADA TOSHIYUKI;KITAGAWA HIDEMASA;ISHIDA SUMI;KAWANA HIDEO
分类号 G11B20/14;H03L7/06;H04L7/02;H04L7/033 主分类号 G11B20/14
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