发明名称 INPUT AND OUTPUT CONTROL SYSTEM
摘要 PURPOSE:To prevent the double transmission of the same data and the omission of a data block in a retrial mode by giving data blocks to the data blocks which are transferred to a main memory respectively and controlling these data blocks according to the data numbers. CONSTITUTION:A data processing system consists of a central processor 1, a main memory 2, a channel 3, a communication controller 4 and a MODEM 5. The data numbers are given to the data blocks included in an input buffer 21 of the controller 4. Then the data number of a message transferred normally is stored in a microprocessor 13 as the latest data number, and the retrial start data number serving as the number to be transferred again in a retrial mode is given to the controller 4. Thus a microprocessor 23 of the controller 4 performs the control based on the received retrial start data number so that the messages having the corresponding data numbers in the buffer 21 are transferred successively again.
申请公布号 JPS61202259(A) 申请公布日期 1986.09.08
申请号 JP19850042630 申请日期 1985.03.06
申请人 HITACHI LTD 发明人 WATABE YASUMASA
分类号 G06F13/12;G06F11/14 主分类号 G06F13/12
代理机构 代理人
主权项
地址