发明名称 PATTERN FOR FET CHIP
摘要 PURPOSE:To increase adhesive strength by forming thick plating layers on bumps shaped to pad sections for a drain electrode and a gate electrode at arbitrary positions, where the thick plating layers are not brought into contact with gold ribbons bonded with a thick plating layer on a source electrode, in a division and contraction manner. CONSTITUTION:Divided thick plating layers 6 having the same shape are formed at desired positions on a source electrode 3 and pad sections for a drain electrode 4 and a gate electrode 5. The width of the divided thick plating layers 6 on the drain electrode 4 and the gate electrode 5 is made the same as the thick plating layers 6 on the source electrodes 3, and length can be set arbitrarily up to positions where the thick plating layers are not brought into contact with gold ribbons 7 bonded with the thick plating layers 6 on the source electrode 3 from pad ends. Accordingly, when a FET chip is bonded with the gold ribbons 7 in a turning-upside-down manner, the thick plating layers 6 on the drain electrode 4 and the gate electrode 5 are buried properly into the gold ribbons 7 in the same manner as the upper section of the source electrode 3 because the thick plating layers 6 are divided and contracted, thus improving adhesive strength.
申请公布号 JPS61201477(A) 申请公布日期 1986.09.06
申请号 JP19850043947 申请日期 1985.03.04
申请人 MITSUBISHI ELECTRIC CORP 发明人 WATASE MANABU
分类号 H01L29/812;H01L21/338;H01L21/60;H01L23/48;H01L29/80 主分类号 H01L29/812
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