| 摘要 |
PURPOSE:To increase the working speed of the title transistor by a method wherein the impurity of a Group III element, which is implanted in such a way as to become the maximum concentration in the region in the lower direction of the active layer, is contained in the transistor. CONSTITUTION:Resists, which are used as masks 14a, are provided on a substrate 1, Si is ion-implanted and an active layer 4 is formed. After that, the resists 14a are removed and a region 9 is formed in the lower direction of the active layer 4 by performing an ion- implantation of B in the whole surface of the substrate 1. Then, a silicon oxide film or other insulating film is coated on the whole surface of the substrate 1 and an activation of the implanted Si ions is performed. Then, this protective film is removed and after a layer 11 and a film 12 are coated in order on the surface of the substrate 1, a layer 13 is formed by evaporation on the film 12. Then, an etching is performed on the layer 11 and the film 12 using the layer 13 as a mask and an electrode 8 is formed. Subsequently, masks 14 are provided outside the region of the substrate 1, Si ions are implanted in the substrate 1 using the resists 14b and the layer 13 as masks, and an N-type region 15 and an N-type region 16 are formed. Then, the resists 14b are removed, the layer 13 and the film 12 are removed, an annealing is performed on the N-type regions 15 and 16, an ohmic metal film 6 and an ohmic metal film 7 are coated, and the source electrode and the drain electrode are formed. |
