ARRANGEMENT OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PURPOSE:To reduce any voltage decline by a method wherein an arrangement restricted region is set up by means of converting the reference values of resistance between sources in WOR net into wiring length to arrange the gates with source pins in WOR net in the restricted region. CONSTITUTION:Multiple cell rows 6 are formed on an LSI chips to arrange cells comprising logic gates on the cell rows. The wiring to be two layers wiring is performed in an Al 1 layer for the wiring in the lateral direction while in Al 2 layers for the wiring in the longitudinal direction. Firstly a reference value of resistance between sources in WOR net is converted into a wiring length in terms of the resistance value per unit of each wiring layer. Secondly assuming the values converted into wiring length of Al 1 and Al 2 respectively to be lx and ly, an arrangement restricted diamond region 4 with diagonal lines of lx and ly is set up. When cells containing gates 2 with source pin in WOR net are arranged in the diamond region 4, any wiring resistance to be decided by wiring process may be contained in the range of reference values unless the wiring is detoured.