| 摘要 |
PURPOSE:To improve the reliability by connecting an output terminal of an original signal oscillating circuit to an input terminal of a frequency division circuit and connecting an output terminal of a timing pulse generating circuit to a reset terminal of the frequency division so as to obtain a reference signal neglecting the delay in the timing pulse at all times. CONSTITUTION:The original oscillating circuit 2 consists of inverters Q1, Q2 and a crystal vibrator X and as the frequency division circuit 1, general-purpose counter ICs such as 74LS92 or 74LS163 are used. The timing pulse generating circuit 3 depends on a keyed APC circuit and a digital signal processing circuit or the like using the reference signal generating circuit. An original signal S1 is impressed to an input terminal 11 of the frequency division circuit 1. The reset state of the circuit 1 is released only when the timing pulse S2 fed to the reset terminal is positive and the circuit 1 applies 1/n frequency division to the original signal S1 and outputs a signal S3 at its output terminal 13.
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