| 摘要 |
PURPOSE:To minimize number of circuit components and to detect the sequence of a high speed input data by inputting an output of a shift register to an address input of the 2nd memory and outputting a trigger signal when the sequence of input data is coincident with a trigger map data. CONSTITUTION:An identification code whether an input data 20 is a trigger data or not is set to a memory 1. Output data 1A-1E of the memory 1 are inputted to shift registers 2-6 by an identification code in 5-bit corresponding to the input data 20 and shifted in order by using a clock signal delayed by a delay circuit 10. Data are set to the memories 7, 8 so that output data of the memories 7, 8 are logical 1 when the address is designated by the expected identification data. When the 5-bit identification codes are all expected identification codes at outputs 21-24 of the shift register, the output of the memories 7, 8 goes to logical 1, resulting that the output of an AND gate 9 is logical 1, logical 1 is outputted to a trigger output terminal 1 to detect the trigger data.
|
