| 摘要 |
PURPOSE:To realize the CMOS circuit of no latch-up and no malfunction caused by parasitic bi-polar elements, by a method wherein this circuit is constructed by connecting the output terminal only to an N<+> diffused layer. CONSTITUTION:The title device is composed of an N-type semiconductor single crystal substrate 13, P-type diffused regions 14 of N-channel regions, P<+> diffused layers 15 of P-channel source or drain regions, N<+> diffused layers 16 of N- channel source or drain regions, gate electrode conductors 17, and gate insulation films 18. A power source V1 is connected to the source (contact 1) of a P- channel MOS transistor T1, and a signal I1 is inputted to the gate (contact 2). The base of an NPN transistor T2 is connected to the drain (contact 3), the collector of the transistor T2 to the power source V1, and the emitter (contact 5) to the drain of an N-channel MOS transistor T3. The source of the transistor T3 is grounded (contact 6), and a signal I2 is inputted to the gate, thus making the contact 5 as the output terminal O1. |
