| 摘要 |
PURPOSE:To realize multiplexing easily without damaging the economization by cascading plural memory devices and writing and reading the same data in and from the same addresses of all memory devices at the same timing. CONSTITUTION:Error checkers 13, memory multiplexing control circuits 14, and multiplexing control signals 6-1-6-(n-1) cascading adjacent memory devices are provided, and the same data is written or read in and from the same addresses of all memory devices 4-1-4-n at the same timing, and data is written or read in or from the first memory device if the first memory device is normal; but if data error is detected, the abnormality of the first memory device is reported to the second memory device by a multiplexing signal to write or read data in or from the second memory; and if the first - the (i-1)th memory devices are abnormal, data is written in or read from the i-th memory device. Thus, the memory multiplexing operation is performed.
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