| 摘要 |
PURPOSE:To execute efficiently even programs requiring the synchronous control of processings of data arrays, by providing a data flow processor with a data flow counting circuit. CONSTITUTION:When a data flow counting instruction is operated, 5 address data of picture elements a41-a45 are generated as a data array A by a program. This instruction has first value '0' as the state, and address data of picture elements a41-a45 are outputted as a data array C as it is when these data arrive successively, and the internal state value is counted up successively by one. When data of the leveling processing result of picture elements a41-a45 comes as a data array B, the data flow counting instruction outputs the data array B as a data array D as it is, and the internal state value is counted down successively by one. When 5 data arrays A come and 5 data arrays B come late, the internal state value is returned to 0, and the data flow counting instruction outputs control data E. Thus data E is used as synchronous data which generates address data of picture elements a51-a56.
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