| 摘要 |
PURPOSE:To design the titled circuit so as not to be affected easily by a local fault and to relieve the load of the software by using the hardware so as to synchronize arithmetic units subject to multiplexing. CONSTITUTION:When a timing of a synchronizing signal SA of the own system is led more than the timing of a synchronizing signal SB of the other system, a delete signal is latched through the operation of a phase information latch circuit 23 and the signal is sent to a counter 10 as phase information 24 to delete the count of the counter 10 in matching with a counter correction timing 22 thereby retarding the timing of the signal SA. As the signal SB approaches the signal SA, the 'delete' signal is changed sequentially into 'slight delete' and 'minute delete' so as to decrease the deleted count by one operation and the SA is approached to the SB smoothly for synchronization. |
