发明名称 |
METHOD OF ADDRESSING RANDOM ACCESS MEMORY AS DELAY LINE AND SIGNAL PROCESSOR CONTAINING SAME DELAY LINE |
摘要 |
<p>A random access memory is used to realize a sequence of delay lines (40, 46, 48, 50). The delay lines are linked so that a common end point of two delay lines can be addressed in a read/modify/write operation. Furthermore, the address step between two successive data elements of the delay line is increased, so that the new address must be calculated modulo the length of the consecutive zone reserved for the delay lines. It has been found that in many cases the incrementation step between the various read addresses has a value which can be expressed in a number of bits which is smaller than the number of bits necessary to express the length of the consecutive memory zone itself.</p> |
申请公布号 |
JPS61196340(A) |
申请公布日期 |
1986.08.30 |
申请号 |
JP19860037549 |
申请日期 |
1986.02.24 |
申请人 |
PHILIPS GLOEILAMPENFAB:NV |
发明人 |
EDEII ARUBERUTO MARIO ODEIKU |
分类号 |
G11C19/00;G06F5/10;G06F12/00;G06F12/02;G11C7/00;G11C8/04 |
主分类号 |
G11C19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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