发明名称 REFRESHING CONTROLLER FOR DYNAMIC MEMORY
摘要 PURPOSE:To reduce the power consumption of a dynamic memory during refreshing and to access the memory efficiently by supplying electric power to a bank which is already used, a bank which is used at present, and a bank to be used next and performing refreshing operation. CONSTITUTION:Band selection signals Ba, Bb, and Bc outputted by a decoder 11 are inputted to set terminals Sb, Sc, and Sd of a bank address latch 30 respectively. The latch 30 is reset with a common resetting signal RST and after this resetting is reset, the 1st rises of the bank selection signals Ba, Bb, and Bc are latched individually to hold latch contents until a next reset signal RST is inputted. Namely, only banks corresponding to relay circuits whose contacts are closed are supplied with a source voltage VD as to the banks B, C, and D although a bank A is supplied with the source voltage VD at any time.
申请公布号 JPS61194699(A) 申请公布日期 1986.08.29
申请号 JP19850033987 申请日期 1985.02.22
申请人 FUJI XEROX CO LTD 发明人 SHIGETA YOSHIHARU
分类号 G11C11/406;G11C11/34 主分类号 G11C11/406
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