发明名称 RECEIVING CIRCUIT
摘要 PURPOSE:To obtain a correct output signal even when a reception signal subject to chattering by using a counter circuit so as to detect a consecutive time of an input signal when a logical input and a contact input are received and giving an output when the time is a prescribed value or above. CONSTITUTION:A signal inputted from an external circuit via an input signal 2 is isolated by a buffer circuit 3 and inputted to a counter circuit 4. While the counter circuit 4 counts a specified count, an output is given only when the input signal is consecutive. Thus, when an input signal subject to chattering, or an unnecessary signal is generated due to noise, the signal is not fetched in the internal circuit. The count time is controlled by a clock signal 5 and set to an optional time. On the other hand, when the input signal is consecutive for a prescribed time and it is regarded as a normal input signal, the counter circuit 4 gives a signal, which is stored in a storage circuit 6. Then the held data is outputted to the internal circuit via an output signal 9.
申请公布号 JPS61194915(A) 申请公布日期 1986.08.29
申请号 JP19850034452 申请日期 1985.02.25
申请人 TOSHIBA CORP 发明人 YAMADA MICHIAKI;OGAWA MASAKATSU
分类号 H04L25/08;H03K5/01;H03K5/1254;H04L25/03 主分类号 H04L25/08
代理机构 代理人
主权项
地址