| 摘要 |
PURPOSE:To prevent useless power consumption due to a disturbing wave by detecting respectively a pattern of the first half bit of an n-bit message synchronizing pattern and a pattern of the latter half bit to start and release the reset of a microprocessor internal clock. CONSTITUTION:A microprocessor having an internal clock control is provided and a received message synchronizing pattern is detected for communication. The pattern 2 with the first half j bits in the received n-bit message synchronizing pattern and the pattern 6 of the latter half (n-j)-bits (n>j), and the pattern 1 of a prescribed j bit and the pattern 5 of (n-j)-bits are compared respectively by comparator circuits 3, 7. When the first half j bit pattern and the prescribed j bit pattern are coincident, the internal clock of the microcomputer 14 is started and when the latter half (n-j)-bit pattern and the prescribed (n-j)-bit pattern are coincident, the reset of the said microprocessor is released. |
